1. Field
Example embodiments of the following description relate to a method and apparatus for processing a vertex, and more particularly, to a method and apparatus for processing a vertex that may selectively fetch attribute information of the vertex and shade the fetched attribute information.
2. Description of the Related Art
A tile-based rendering (TBR) architecture among technologies for realizing three-dimensional (3D) graphics enables 3D visualization in various fields ranging from mobile devices to precise scientific simulations. The TBR architecture may perform fragment processing in a tile buffer that is an on-chip memory of a graphics pipeline, and may transmit a final result to an off-chip memory of the graphics pipeline. Accordingly, a scene buffer for storing a result of the TBR and a result of a tile binning operation is additionally required. Here, to increase realism of 3D graphics, when a number of used vertexes is increased, a bandwidth of an off-chip memory that is required to fetch initial vertex data, and a requirement for a bandwidth of an off-chip memory connected to the scene buffer may be rapidly increased. In other words, costs incurred by accessing the off-chip memory and overhead costs incurred by the tile binning operation may be increased. Accordingly, there is a desire to improve a data processing performance by reducing an induction of a memory bandwidth caused by the TBR architecture.